The present invention relates generally to a radio frequency identification (RFID) device, and more particularly to initializing a memory of an RFID device using an offset voltage.
An RFID device has numerous applications. For example, an RFID device may be utilized in a physical distribution managing system, a user identification system, an electronic money system, and a traffic system.
The physical distribution managing system performs cargo distribution and inventory control using an integrated circuit (IC) tag where data are recorded instead of utilizing a delivery slip. The user identification system manages exit and entry control using an IC card on which personal information is recorded.
A nonvolatile memory, for example a ferroelectric memory, may be used as a memory used in an RFID tag.
Generally, the data processing speed of a Ferroelectric Random Access Memory (FeRAM) is similar to that of Dynamic Random Access Memory (DRAM). Also, the FeRAM is a non-volatile memory device, and therefore, the data stored in the FeRAM is conserved even after power is turned off.
An FeRAM device, having a structure similar to that of a DRAM device, includes capacitors made of a ferroelectric substance. Further, the FeRAM device has a high residual polarization allowing for data retention even when an electric field is removed.
FIG. 1 is a circuit diagram showing a cell array unit of a conventional RFID device. The cell array unit shown in FIG. 1 comprises a cell array CA, a sense amplifier SA1, and a bit line equalizer 10.
The cell array CA includes a pair of bit lines BL, /BL, a plurality of word lines WL, a plurality of plate lines PL, and a plurality of unit cells UC positioned at intersections of the word lines WL and the bit lines BL, /BL between a word line WL and a plate line PL.
A unit cell UC connected to the bit line BL and a unit cell connected to the bit line /BL store conjugate data D, /D, respectively. A voltage sensed in the cell array is applied to the bit line BL, and a reference voltage REF is applied to the bit line /BL.
Each of the unit cells UC includes a switching element T and a ferroelectric capacitor FC. The ferroelectric capacitor FC is connected between the plate line PL and the switching element T. The switching element T is connected between the bit line BL (or the bit line /BL) and the ferroelectric capacitor FC. The switching element T may comprise, for example, a MOS transistor. A gate of the MOS transistor (switching element T) is connected to the word line WL.
The sense amplifier SA1 is connected between the paired bit lines BL and /BL, and activated by a sense amplifier enable signal SEN. When the sense amplifier SA1 is activated by the sense amplifier enable signal SEN, the sense amplifier SA1 senses and amplifies a voltage difference of the paired bit lines BL and /BL.
The bit line equalizer 10 includes NMOS transistors N1˜N3. The NMOS transistor N1 is connected between a ground voltage terminal VSS and the bit line BL, the NMOS transistor N2 is connected between the paired bit lines BL and /BL, and the NMOS transistor N3 is connected between the ground voltage terminal VSS and the bit line /BL. As shown in FIG. 1, the respective gates of the NMOS transistors N1˜N3 are connected to a bit line equalizing signal BLEQ. When the bit line equalizing signal BLEQ is activated, the NMOS transistors N1˜N3 are turned on thereby equalizing the paired bit lines BL and /BL.
In the cell array CA, the capacitance CBL of the bit line BL has a capacitance Ci.
FIG. 2 is a graph showing a voltage waveform of the bit line in the cell operation of the cell array unit of FIG. 1.
The bit line equalizer 10 is activated, before activating the sense amplifier SA1, to equalize voltage levels of the bit line BL and the bit line /BL (REF). After the sense amplifier SA1 is activated, the bit line equalizer 10 is inactivated, and the voltage levels of the bit lines BL and /BL are different from each other.
In the initial cell operation, the capacitance Ci of the bit lines BL and /BL is the same. Also, since the amount of charges stored in each cell is the same, the sensing voltage applied to the bit line BL and /BL is the same.
FIG. 3 is a diagram showing an offset voltage of the sense amplifier of FIG. 1.
In the conventional cell array unit, the voltage levels of the bit line BL and the bit line /BL (REF) are the same before the sense amplifier SA1 is activated. That is, the voltage level of the bit line BL inputted to a positive (+) terminal of the sense amplifier SA1 is the same as the reference voltage level of the bit line /BL inputted to a negative (−) terminal of the sense amplifier SA1.
When the voltage level of the bit line BL and the bit line /BL are the same, an offset voltage Voffset between the positive (+) terminal and the negative (−) terminal of the sense amplifier SA1 is “0V.” That is, there is no offset voltage Voffset between the bit line BL and the bit line /BL.
It is necessary to set initial data stored in the memory of the RFID device as “0” because the memory of the RFID device is designed on the supposition that the initial data stored in the unit cells are all “0.”
However, since the offset voltage is not generated in the sense amplifier of the conventional cell array unit, data “0” and “1” are stored together in the unit cells. As a result, a fail occurs when the memory of the RFID device is designed on the supposition that the initial data stored in the unit cells are all “0.”